The present invention relates to a semiconductor integrated circuit employing complementary MOS transistors.
Complementary MOS (hereinafter referred to as "CMOS") integrated circuits which employ both of n-channel field effect transistors and p-channel transistors have been widely utilized because they consume less electric power. In a CMOS integrated circuit, n-channel field effect transistors and p-channel field effect transistors are formed on different surface regions of a semiconductor substrate. For example, in the case where an n-type semiconductor substrate is employed, p-channel transistors are formed on a certain area of the substrate while a p-type well region is provided on another area of the substrate and n-channel transistors are formed on the well region. In order to arrange the transistors at high density, the above certain region and the well region are adjacently located and power supply wirings are arranged both outer sides of the adjacent certain region and the well regions. While signal wirings for carrying logic signals are extended in the direction normal to that of the power supply wirings through the above two regions. According to this arrangement, the power supply wirings are arranged in parallel and the signal wirings are also arranged in parallel in each wiring group, and hence design in the wiring is easy. The signal wirings are extending beyond the power supply wirings from the transistor region and therefore the signal wirings inevitably overlap the power supply wirings. Therefore, in the case where the power supply wirings are made of low-resistive metal, the signal wirings are usually made of polycrystalline silicon in order to achieve the multilayer wirings with ease. However, as is well known, the resistance of the polycrystalline silicon is relatively large and hence the signal transmission time through the signal wirings is large, resulting in low speed operation. Moreover, the above overlap of the signal wirings on the power supply wirings and the formation of the power supply wirings outside the transistor region make it difficult to form the circuit with the high integration structure.